A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having shallow trench isolation (STI) and its manufacture method.
B) Description of the Related Art
Local oxidation of silicon (LOCOS) is known as one method for the element isolation of a semiconductor device.
According to LOCOS technique, a silicon oxide film is formed on a silicon substrate as a buffer layer, thereafter a silicon nitride film as an oxidation prevention film is formed, the silicon nitride film is patterned and then the surface of the silicon substrate is thermally oxidized.
While the silicon substrate is thermally oxidized, oxidizing species such as oxygen and moisture invade the buffer silicon oxide film. As a result, the silicon substrate surface under the silicon nitride film is oxidized and silicon oxide regions having a shape called a bird's beak are formed. These bird's beak regions cannot be used substantially as an element forming region (active region) so that the area of the active region is reduced.
If the surface of a silicon substrate is thermally oxidized by using a silicon nitride film pattern having openings of various sizes, the thickness of a silicon oxide film formed on the silicon substrate surface in an area corresponding to an opening of a smaller size is thinner than that of a silicon oxide film formed in an area corresponding to an opening of a lager size. This phenomenon is called thinning.
The area not used as the active region in the whole area of a semiconductor substrate increases because of bird's beaks and thinning which occur more often as semiconductor devices are made finer. Namely, since a ratio of the active region to the whole substrate area is substantially lowered, high integration of semiconductor devices is hindered.
Trench isolation (TI) technique is know as the technique of forming active regions by which a trench is formed in the surface layer of a semiconductor substrate and insulating material or polysilicon is filled in the trench. This method has been used bipolar transistor LSIs which require a deep isolation region.
Application of trench isolation technique to MOS transistor LSIs is prevailing because of no bird's beak and thinning. Isolation for a MOS transistor LSI does not require as deep isolation as that of a bipolar transistor LSI and can be realized by a relatively shallow trench of about 0.1 to 1.0 μm. This is called a shallow trench isolation (STI) structure.
With reference to FIGS. 9A to 9H, an STI process will be described.
As shown in FIG. 9A, on the surface of a silicon substrate 1, a silicon oxide film 2 having a thickness of, e.g., 10 nm is formed by thermal oxidation. On this silicon oxide film 2, a silicon nitride film 3 having a thickness of e.g., 100 to 150 nm is formed by chemical vapor deposition (CVD). The silicon oxide layer 2 functions as a buffer layer for relaxing a stress between the silicon substrate 1 and silicon nitride film 3. The silicon nitride film 3 is functions also as a stopper layer during a later polishing process.
A resist pattern 4 is formed on the silicon nitride film 3. An opening defined by the resist pattern 4 defines an area in which the active region is formed. The region of the silicon substrate under the resist pattern becomes an active region where device elements are formed.
By using the resist pattern 4 as an etching mask, the silicon nitride film 3 exposed in the opening and the underlying silicon oxide film 2 and silicon substrate 1 are etched to a depth of, e.g., about 0.5 μm by reactive ion etching (RIE) to form a trench 6. Thereafter, the resist pattern 4 is removed.
As shown in FIG. 9B, the silicon substrate surface exposed in the trench 6 is thermally oxidized to form a silicon oxide film 7 having a thickness of, e.g., 10 nm.
As shown in FIG. 9C, burying the trench, a silicon oxide layer 9 is deposited over the silicon substrate, for example, by high density plasma (HDP) CVD. In order to make dense the silicon oxide film 9 as the isolation region, the silicon substrate is annealed, for example, in a nitrogen atmosphere at 900 to 1100° C.
As shown in FIG. 9D, by using the silicon nitride film 3 as a stopper, the silicon oxide layer 9 is etched downward by chemical mechanical polishing (CMP) or reactive ion etching (RIE). The silicon oxide film 9 is left only in the trench defined by the silicon nitride film 3. At this stage, annealing may be performed for making silicon oxide dense.
As shown in FIG. 9E, the silicon nitride film 3 is removed by using hot phosphoric acid. Next, the buffer silicon oxide film 2 on the surface of the silicon substrate 1 is removed by using dilute hydrofluoric acid. At this time, the silicon oxide film 9 buried in the trench is also etched.
As shown in FIG. 9F, the surface of the silicon substrate 1 is thermally oxidized to form a sacrificial silicon oxide film 22 on the silicon substrate 1 surface. Impurity ions of a predetermined conductivity type are implanted into the surface layer of the silicon substrate 1 via the sacrificial silicon oxide film, and activated to form wells 10 of the predetermined conductivity type in the silicon substrate 1.
The sacrificial silicon oxide film 22 is thereafter removed by using dilute hydrofluoric acid. While the sacrificial silicon oxide film is removed, the silicon oxide layer 9 is also etched by the dilute hydrofluoric acid. By a plurality of hydrofluoric acid processes, the silicon oxide layer 9 buried in the trench is etched so that a dug divot or indent is formed along the side of the active region.
As shown in FIG. 9G, the surface of the exposed silicon substrate is thermally oxidized to form a silicon oxide film 11 having a desired thickness which film is used as the gate insulating film. A polysilicon layer 12 is deposited over the silicon substrate 1, and patterned to form a gate electrode. Impurity ions of the conductivity type opposite to that of the wells 10 are implanted and activated to form source/drain regions. If necessary, side wall spacers are formed on the side walls of the gate electrode, and impurity ions are again implanted and activated to form high impurity concentration source/drain regions.
FIG. 9H shows the characteristics of drain current relative to gate voltage of a transistor manufactured as above. The abscissa represents gate voltage and the ordinate represents drain current. A curve r shows the characteristic of a normal transistor. A curve h shows the characteristics of a transistor formed by the above-described processes. As seen from the curve h, the drain current starts flowing at a lower gate voltage. This analysis results in that a parasitic transistor turning on at a low threshold voltage is added.
If the shoulder S of the isolation region 9 is etched and divots or recesses are formed as shown in FIG. 9G, the shoulder of the active region of the silicon substrate is surrounded by the gate electrode not only from the upper surface of the active region but also from the side thereof. As voltage is applied to the gate electrode having such a shape, the shoulder of the active region undergoes an electric field concentration so that a transistor having a lower threshold voltage is formed. This parasitic transistor forms the hump characteristics indicated by the curve h shown in FIG. 9H.
As seen from the curve h, the drain current at a higher gate voltage is lower than that of the curve r. As heat treatment is performed in order to make dense the silicon oxide buried in the trench, the silicon oxide layer 9 contracts so that the active region surrounded by the silicon oxide film 9 receives a compression stress.
As the compression stress is applied, the mobility of electron/hole in the active region of the silicon substrate 1 may lower, which reduces the saturated drain current. As the element is made finer and the area of the active region is made small, the influence of the compression stress increases.
In IEDM 1988, pp. 92-95, B. Davari et al. have proposed to implant ions into the shoulder of an active region in order to suppress the hump characteristics.
Another method has been proposed to round the shoulder of an active region through thermal oxidation in order to suppress the hump characteristics. Since the shoulder is rounded and the electric field concentration is relaxed, the influence of a parasitic transistor can be mitigated.
In IEDM 1992, pp. 57-60, Pierre C. Fazan et al. have proposed to form insulating side wall spacers on the side walls of an isolation silicon oxide film protruding from an upper surface of a silicon substrate to thereby bury divots.
Although STI is suitable for the microfine structure of semiconductor devices, there occur problems specific to STI. New techniques capable of solving the problems specific to STI have been desired to date.